1. Field of the Invention
The present invention relates to electronic circuitry and, more particularly, to an apparatus and method for generating phase-controlled clock signals.
2. Background Information and Related Art
Microprocessors typically include a conventional phase-lock loop clock generator for generating a processor clock signal in response to an external system clock signal. Preferably, the external system clock signal operates at its maximum possible frequency, as determined largely by the system design. For example, the optimum external system clock frequency may be 66 MHz, while the optimum internal clock frequency of a microprocessor may be 100 MHz, which is one and one-half times the optimum external system clock frequency.
However, conventional phase-lock loop generators cannot operate in a 3:2 mode. That is, they cannot generate an internal processor clock signal that has a 3:2 frequency ratio to the external system clock signal. Therefore, the previously described optimum clock signal frequencies cannot be obtained using conventional phase-lock loop generators. Accordingly, there is a great need for an improved clock regenerator that is capable of performing an n:m frequency ratio of the processor clock signal to the external system clock signal, where n and m are integers other than one.
Furthermore, microprocessors typically include some logic, such as a bus interface unit, that operates at the external system clock frequency. Therefore, there is a great need for an improved clock regenerator that generates and distributes both the previously mentioned high-speed internal processor clock signal and an internal system clock signal throughout the microprocessor. Both of these clocks should be distributed throughout the microprocessor using the same distribution network. Therefore, the improved clock generator should be capable of generating and distributing multiple in-phase clock signals within the microprocessor.
Finally, even if an improved clock regenerator could be implemented, either one of two substantially equal, but 180 degrees out of phase, processor clock signals will be generated each time a reset or power-up event occurs. This event produces testing errors and degrades performance of systems having multiple processors that must operate in synchronization with each other. Accordingly, there is a great need for an improved clock regenerator that generates an internal processor clock signal that is consistently synchronized with the external system clock signal.